Verification of Asynchronous Circuits using Timed Automata
نویسندگان
چکیده
منابع مشابه
Verification of Asynchronous Circuits using Timed Automata
In this work we apply the timing veriication tool OpenKronos, which is based on timed automata, to verify correctness of numerous asynchronous circuits. The desired behavior of these circuits is speciied in terms of signal transition graphs (STG) and we check whether the synthesized circuits behave correctly under the assumption that the inputs satisfy the STG conventions and that the gate dela...
متن کاملTiming analysis of asynchronous circuits using timed automata
In this paper we present a method for modeling asynchronous digital circuits by timed automata The constructed timed automata serve as mechanical and veri able objects for asynchronous sequential machines in the same sense that untimed automata do for synchronous machines These results combined with recent results concerning the analysis and synthesis of timed automata provide for the systemati...
متن کاملVerification of Bounded Delay Asynchronous Circuits with Timed Traces
In this paper, we extend the verification method based on trace theory by Dill et al. such that it can handle bounded delay asynchronous circuits and check certain liveness properties as well as safety properties. We use time Petri nets to model both bounded delay circuits and timed properties to be verified. Some experimental results are also shown to demonstrate the proposed method.
متن کاملAsynchronous Communication Mechanisms Using Self-Timed Circuits
Two asynchronous data communication mechanisms (ACMs) using self-timed circuits are presented. Mutual exclusion elements are used to concentrate potential metastability to discrete points so that it can be resolved entirely within the ACMs themselves. Self-timed circuits allow the minimisation of the interface between the reader and writer processes and the ACMs. Initial analysis shows that the...
متن کاملVerification of Printer Datapaths Using Timed Automata
In multiprocessor systems with many data-intensive tasks, a bus may be among the most critical resources. Typically, allocation of bandwidth to one (high-priority) task may lead to a reduction of the bandwidth of other tasks, and thereby e ectively slow down these tasks. WCET analysis for these types of systems is a major research challenge. In this paper, we show how the dynamic behavior of a ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: Electronic Notes in Theoretical Computer Science
سال: 2002
ISSN: 1571-0661
DOI: 10.1016/s1571-0661(04)80468-7